/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:52 2011
//--
//-- Source file: dma_core_axim_resp.v
//---------------------------------------------------------



module dma_axi32_core0_axim_resp(clk,reset,slverr,decerr,clr,clr_last,ch_num_resp,resp_full,AID,AVALID,AREADY,RESP,ID,VALID,READY,LAST);

   parameter                  CMD_DEPTH = 8;
      
   input               clk;
   input               reset;

   output               slverr;
   output               decerr;
   output               clr;
   output               clr_last;
   output [2:0]           ch_num_resp;
   output               resp_full;
   
   
   input [`CMD_BITS-1:0]      AID;
   input               AVALID;
   input               AREADY;
   input [1:0]               RESP;
   output [`CMD_BITS-1:0]     ID;
   input               VALID;
   input               READY;
   input               LAST;


   
   parameter                  RESP_SLVERR = 2'b10;
   parameter                  RESP_DECERR = 2'b11;


   wire               clr_pre;
   wire [2:0]               ch_num_resp_pre;
   wire               clr_last_pre;
   wire               slverr_pre;
   wire               decerr_pre;
   reg [2:0]               ch_num_resp;

   wire               resp_push;
   wire               resp_pop;
   wire               resp_empty;
   wire               resp_full;
   wire [`CMD_BITS-1:0]       ID;
   

   assign               resp_push       = AVALID & AREADY;
   assign               resp_pop        = VALID & READY & LAST;
   
   assign               clr_pre         = resp_pop;
   
   assign               ch_num_resp_pre = ID[2:0] ;
   
   assign               slverr_pre      = clr_pre & RESP == RESP_SLVERR;
   assign               decerr_pre      = clr_pre & RESP == RESP_DECERR;
   
   assign               clr_last_pre    = clr_pre & ID[3];
   
   prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(clr_pre), .dout(clr));
   prgen_delay #(1) delay_clr_last(.clk(clk), .reset(reset), .din(clr_last_pre), .dout(clr_last));
   prgen_delay #(1) delay_slverr(.clk(clk), .reset(reset), .din(slverr_pre), .dout(slverr));
   prgen_delay #(1) delay_decerr(.clk(clk), .reset(reset), .din(decerr_pre), .dout(decerr));
   
   always @(posedge clk or posedge reset)
     if (reset)
       ch_num_resp <= #1 3'b000;
     else if (clr_pre)
       ch_num_resp <= #1 ch_num_resp_pre;
   


   prgen_fifo #(`CMD_BITS, CMD_DEPTH) 
   resp_fifo(
         .clk(clk),
         .reset(reset),
         .push(resp_push),
         .pop(resp_pop),
         .din(AID),
         .dout(ID),
         .empty(resp_empty),
         .full(resp_full)
         );

   
endmodule





